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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_test_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__pdm__pcm__v2.html">PDM_PCM_v2   (PDM-PCM Converter v2)</a> &raquo; <a class="el" href="group__group__pdm__pcm__data__structures__v2.html">Data Structures</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>PDM-PCM Test Mode configuration. </p>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:aaeca75971b46a735aa82ca9a4dc32fdc"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__test__config__t.html#aaeca75971b46a735aa82ca9a4dc32fdc">drive_delay_hi</a></td></tr>
<tr class="memdesc:aaeca75971b46a735aa82ca9a4dc32fdc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface drive delay on the high phase of the PDM interface clock.  <a href="#aaeca75971b46a735aa82ca9a4dc32fdc">More...</a><br /></td></tr>
<tr class="separator:aaeca75971b46a735aa82ca9a4dc32fdc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40e72956f9a2ef2c37461da5766ab0ec"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__test__config__t.html#a40e72956f9a2ef2c37461da5766ab0ec">drive_delay_lo</a></td></tr>
<tr class="memdesc:a40e72956f9a2ef2c37461da5766ab0ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interface drive delay on the low phase of the PDM interface clock.  <a href="#a40e72956f9a2ef2c37461da5766ab0ec">More...</a><br /></td></tr>
<tr class="separator:a40e72956f9a2ef2c37461da5766ab0ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a37443460ff4e51026c954426770765c5"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__test__config__t.html#a37443460ff4e51026c954426770765c5">mode_hi</a></td></tr>
<tr class="memdesc:a37443460ff4e51026c954426770765c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pattern generator mode on the high phase of the PDM interface clock.  <a href="#a37443460ff4e51026c954426770765c5">More...</a><br /></td></tr>
<tr class="separator:a37443460ff4e51026c954426770765c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac41864acd726923379709a58eceecd4a"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__test__config__t.html#ac41864acd726923379709a58eceecd4a">mode_lo</a></td></tr>
<tr class="memdesc:ac41864acd726923379709a58eceecd4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pattern generator mode on the low phase of the PDM interface clock.  <a href="#ac41864acd726923379709a58eceecd4a">More...</a><br /></td></tr>
<tr class="separator:ac41864acd726923379709a58eceecd4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac76c690654428a83147427b2a440073a"><td class="memItemLeft" align="right" valign="top">uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__test__config__t.html#ac76c690654428a83147427b2a440073a">audio_freq_div</a></td></tr>
<tr class="memdesc:ac76c690654428a83147427b2a440073a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency.  <a href="#ac76c690654428a83147427b2a440073a">More...</a><br /></td></tr>
<tr class="separator:ac76c690654428a83147427b2a440073a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00483dafa146cbbc0b1cb040b338b64d"><td class="memItemLeft" align="right" valign="top"><a id="a00483dafa146cbbc0b1cb040b338b64d"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__test__config__t.html#a00483dafa146cbbc0b1cb040b338b64d">enable</a></td></tr>
<tr class="memdesc:a00483dafa146cbbc0b1cb040b338b64d"><td class="mdescLeft">&#160;</td><td class="mdescRight">enable <br /></td></tr>
<tr class="separator:a00483dafa146cbbc0b1cb040b338b64d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
<a id="aaeca75971b46a735aa82ca9a4dc32fdc"></a>
<h2 class="memtitle"><span class="permalink"><a href="#aaeca75971b46a735aa82ca9a4dc32fdc">&#9670;&nbsp;</a></span>drive_delay_hi</h2>

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          <td class="memname">uint8_t cy_stc_test_config_t::drive_delay_hi</td>
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<p>Interface drive delay on the high phase of the PDM interface clock. </p>
<p>This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm </p>

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<a id="a40e72956f9a2ef2c37461da5766ab0ec"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a40e72956f9a2ef2c37461da5766ab0ec">&#9670;&nbsp;</a></span>drive_delay_lo</h2>

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          <td class="memname">uint8_t cy_stc_test_config_t::drive_delay_lo</td>
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<p>Interface drive delay on the low phase of the PDM interface clock. </p>
<p>This field specifies when a PDM value is driven expressed in clk_if clock cycles. DRIVE_DELAY should be set in the range [0, IF_CTL.CLOCK_DIV]: "0": Drive PDM value 1 clk_if cycle after the rising edge of clk_pdm. "1": Drive PDM value 2 clk_if cycles after the rising edge of clk_pdm. ... "255": Drive PDM value 256 clk_if cycles after the rising edge of clk_pdm </p>

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<a id="a37443460ff4e51026c954426770765c5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a37443460ff4e51026c954426770765c5">&#9670;&nbsp;</a></span>mode_hi</h2>

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          <td class="memname">uint8_t cy_stc_test_config_t::mode_hi</td>
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<p>Pattern generator mode on the high phase of the PDM interface clock. </p>
<p>This field specifies the type of pattern driven by the generator: "0": constant 0's "1": constant 1's "2": alternating 0's and 1's (clock pattern) "3": sine wave </p>

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<a id="ac41864acd726923379709a58eceecd4a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac41864acd726923379709a58eceecd4a">&#9670;&nbsp;</a></span>mode_lo</h2>

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          <td class="memname">uint8_t cy_stc_test_config_t::mode_lo</td>
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<p>Pattern generator mode on the low phase of the PDM interface clock. </p>
<p>This field specifies the type of pattern driven by the generator: "0": constant 0's "1": constant 1's "2": alternating 0's and 1's (clock pattern) "3": sine wave </p>

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<a id="ac76c690654428a83147427b2a440073a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ac76c690654428a83147427b2a440073a">&#9670;&nbsp;</a></span>audio_freq_div</h2>

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          <td class="memname">uint8_t cy_stc_test_config_t::audio_freq_div</td>
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<p>Frequency division factor (legal range [3, 13]) to obtain audio frequency from the PDM clock frequency. </p>
<p>This field determines the frequency of the sine wave generated by the pattern generator when MODE=3. The formula is below: Sine wave Frequency = PDM clock frequency / 2p*2^(AUDIO_FREQ_DIV) </p>

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